motorola semiconductor technical data order this document by MC68HC912BD32AD/d ? motorola, inc., 2001 MC68HC912BD32AD addendum to 68hc912bd32 technical data this addendum provides changes to the 68hc912bd32 advance information technical data book (motorola document order number mc68hc912bd32/d rev. 1.0). spi data register (sp0dr) reset value on page 163, there is a discrepancy in the definition of the effect of reset on the sp0dr register. the reset values in the register diagram should be ignored as this register is unaffected by reset. wait i dd in single-chip mode at 10mhz the wait i dd limit in single-chip mode at 10mhz has been changed from 6ma to 8ma. this applies to table 68 on page 258. sp0dr ? spi data register $00d5 bit 7654321bit 0 bit 7654321bit 0 table 68 supply current v dd = 5.0 vdc 5%, v ss = 0 vdc, t a = t l to t h , unless otherwise noted characteristic symbol 8 mhz typical 4 mhz 8 mhz 10 mhz unit wait: (all peripheral functions shut down) single-chip mode w idd 358ma
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